GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 BGA Pin Description
Symbol
A0, A1
An
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
BA, BB, BC,BD, BE, BF,
BG,BH
I
NC
CK
—
No Connect
Clock Input Signal; active high
I
I
I
I
I
I
I
I
I
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
W
E1, E3
E2
Chip Enable; active high
Output Enable; active low
G
Sleep Mode control; active high
ZZ
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
FT
LBO
MCH
MCL
PE
Must Connect Low
I
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Burst Address Counter Advance Enable; active high
ADV
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
I
ZQ
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 2.21 11/2004
3/38
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
