GS88036AT-200 参数 Datasheet PDF下载

GS88018/32/36AT-250/225/200/166/150/133

Simplified State Diagram with G

X

Deselect

W

W

X

W

CW

R

R

First Write

R

CR

First Read

X

CR

CW

W

X

Burst Write

R

CR

W

CW

R

X

Burst Read

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.02 9/2002

10/26

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.