HANBit
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in falling edge to CK rising-setup
time
DQS-in falling edge to CK rising hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
DQS write postamble time
Notes :
1.
2.
3.
Maximum burst refresh of 8.
t
DQSS
t
WPRES
t
WPREH
t
DSS
t
DSH
t
DQSH
t
DQSL
t
DSC
t
IS
t
IH
t
MRD
t
DS
t
DH
t
DIPW
t
PDEX
t
XSW
t
XSA
t
XSR
T
REF
T
QH
T
WPST
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
1.1
16
0.6
0.6
2
10
116
80
200
7.8
0.35
0.25
1.1
1.25
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
15
0.5
0.5
1.75
10
95
75
200
7.8
0.35
0.25
1.1
1.25
HDD32M72B18RPW
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
15
0.5
0.5
1.75
10
1.1
1.25
t
CK
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
75
200
7.8
0.35
0.25
ns
Cycle
us
t
CK
t
CK
4
1
3
t
HZQ
transitions occurs in the same assess time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t
DQSS.
4.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
URL : www.hbe.co.kr
REV 1.0 (August.2002)
9
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
