HANBit
HFDOM40C-xxxSx
3. INTERFACE BUS TIMING
ACCESS SPCIFICATIONS
IDE MODE I/O ACCESS SPECIFICATIONS
In this True IDE Mode the Flash Disk Module protocol and configuration are disabled and only I/O operations to the
Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host.
Table 3.1 IDE Mode I/O Access Mode
Mode
Invalid Mode
Standby Mode
Task File Write
Task File Read
Data Register Write
Data Register Read
Control Register Write
All Status Read
-CE2
L
H
H
H
H
H
L
L
-CE1
L
H
L
L
L
L
H
H
A2-A0
x
x
1-7h
1-7h
0
0
6h
6h
-IORD
x
x
H
L
H
L
H
L
-IOWR
x
x
L
H
L
H
L
H
D15 - D8
High Z
High Z
Don’t Care
High Z
Odd Byte in
Odd Byte out
Don’t Care
High Z
D7
–
D0
High Z
High Z
Data In
Data Out
Even Byte in
Even Byte out
Control In
Status Out
Table 3.2 IDE Mode I/O Read Timing
Parameter
Data Delay after IORD
Data Hold following IORD
IORD Width Time
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
CE Hold following IORD
IOIS16 Delay Falling from Address
Symbol
td (IORD)
th (IORD)
tw (IORD)
tsuA (IORD)
thA (IORD)
tsuCE (IORD)
thCE (IORD)
tdfIOIS16 (ADR)
IEEE Symbol
tlGLQV
tlGHQX
tlGLIGH
tAVIGL
tlGHAX
tELIGL
tlGHEH
tAVISL
0
165
70
20
5
20
35
Min. ns
Max. ns
100
IOIS16 Delay Rising from Address
tdrIOIS16 (ADR)
tAVISH
35
NOTE:
The maximum load on -IOIS16 is 1 LSTTL with 50pF total lo ad. All times are in nanoseconds. Minimum time
from
–WAIT
high to -IORD high is 0nsec, but minimum -IORD width must still be met.
URL : www.hbe.co.kr
REV 1.0 (March.2003)
8 / 10
HANBit Electronics Co., Ltd
.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
