HANBit
HFDOM40C-xxxSx
A0-A10
-CE
-IORD
-IOIS16
Dout
Figure 3.1 IDE Mode I/O Read Timing Example
Table 3.3 IDE Mode I/O Write Timing
Parameter
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
CE Hold following IOWR
IOIS16 Delay Falling from Address
Symbol
tsu(IOWR)
th(IOWR)
twI(OWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tdfIOIS16(ADR)
IEEE Symbol
tDVIWH
tlWHDX
tlWLIWH
tAVIWL
tlWHAX
tELIWL
tlWHEH
tAVISL
Min. ns
60
30
165
70
20
5
20
35
Max. ns
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
NOTE:
The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum
time from
-WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met.
URL : www.hbe.co.kr
REV 1.0 (March.2003)
9 / 10
HANBit Electronics Co., Ltd
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