HANBit
READ CYCLE
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Read Cycle Time
Address Access Time
Chip enable access time
Output enable to Output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output high Z
Output hold from address change
SYMBOL
t
RC
t
ACC
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
CONDITIONS
-70
MIN
70
-
-
-
5
5
0
0
10
MAX
-
70
70
35
-
-
25
25
-
MIN
85
-
-
-
5
0
0
0
10
-85
MAX
-
85
85
45
-
-
35
25
-
-120
MIN
120
-
-
-
5
0
0
0
10
MAX
-
120
120
60
-
-
45
35
-
HMN1M8D
-150
MIN
150
-
-
-
10
5
0
0
10
MAX
-
150
150
70
-
-
60
50
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(T
A
= T
OPR
, V
ccmin
£
V
cc
≤
V
ccmax
)
PARAMETER
Write Cycle Time
Chip enable to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
SYMBOL
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
DW
t
DH1
t
DH2
t
WZ
t
OW
Note 4
Note 4
Note 5
Note 5
Note 1
Note 2
Note 1
Note 1
Note 3
Note 3
CONDITIONS
-70
MIN
70
65
0
65
55
5
15
30
0
10
0
5
MAX
-
-
-
-
-
-
-
-
-
-
25
-
MIN
85
75
0
75
65
5
15
35
0
10
0
0
-85
MAX
-
-
-
-
-
-
-
-
-
-
30
-
-120
MIN
120
100
0
100
85
5
15
45
0
10
0
0
MAX
-
-
-
-
-
-
-
-
-
-
40
-
-150
Min
150
100
0
90
90
5
15
50
0
0
0
5
Max
-
-
-
-
-
-
-
-
-
-
50
-
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either t
WR1
or t
WR2
must be met.
4. Either t
DH1
or t
DH2
must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
5
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
