HANBit
- WRITE CYCLE NO.2 (/CE-CONTROLLED)
*1,2,3,4,5
t
WC
Address
t
AS
/CE
t
WP
/WE
t
DW
D
IN
t
WZ
D
OUT
Data
NOTE:
HMN2568D
t
AW
t
CW
t
WR2
t
DH2
Data-in
Undefined
High-Z
1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either t
WR1
or t
WR2
must be met.
5. Either t
DH1
or t
DH2
must be met.
- POWER-DOWN/POWER-UP TIMING
t
PF
V
CC
4.75
V
PFD
V
PFD
4.25
V
SO
t
FS
t
WPT
/CE
t
DR
V
SO
t
PU
t
CER
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
8
HANBit Electronics Co.,Ltd