欢迎访问ic37.com |
会员登录 免费注册
发布采购

HMS3224Z3-17 参数 Datasheet PDF下载

HMS3224Z3-17图片预览
型号: HMS3224Z3-17
PDF下载: 下载PDF文件 查看货源
内容描述: SRAM模块768KBit ( 32K ×24位) [SRAM MODULE 768KBit (32K x 24-Bit)]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 185 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
 浏览型号HMS3224Z3-17的Datasheet PDF文件第2页浏览型号HMS3224Z3-17的Datasheet PDF文件第3页浏览型号HMS3224Z3-17的Datasheet PDF文件第4页浏览型号HMS3224Z3-17的Datasheet PDF文件第5页浏览型号HMS3224Z3-17的Datasheet PDF文件第6页浏览型号HMS3224Z3-17的Datasheet PDF文件第8页浏览型号HMS3224Z3-17的Datasheet PDF文件第9页浏览型号HMS3224Z3-17的Datasheet PDF文件第10页  
HANBit
HMS3224M3/Z3
TIMING WAVEFORM OF WRITE CYCLE
(/OE = Clock )
t
WC
Address
t
AW
t
WR(5)
/OE
t
CW(3)
/CE
t
AS(4)
t
WP(2)
/WE
t
DW
t
DH
High-Z
t
OHZ(6)
Data In
t
OW
High-Z
Data Out
TIMING WAVEFORM OF WRITE CYCLE
(/OE Low Fixed )
t
WC
Address
t
AW
t
CW(3)
t
WR(5)
/CE
t
AS(4)
t
WP(2)
t
OH
/ WE
t
DW
High-Z
t
DH
Data In
t
WHZ(6,7)
t
OW
High-Z(8)
(10)
(9)
Data Out
Notes
(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
t
WP
is measured from the beginning of write to the end of write.
7
HANBit Electronics Co.,Ltd.