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HMS51232J4A-12 参数 Datasheet PDF下载

HMS51232J4A-12图片预览
型号: HMS51232J4A-12
PDF下载: 下载PDF文件 查看货源
内容描述: SRAM模块2Mbyte ( 512K ×32位) , 68引脚JLCC包装 [SRAM MODULE 2Mbyte (512K x 32-Bit), 68-Pin JLCC Packaging]
分类和应用: 存储静态存储器
文件页数/大小: 6 页 / 163 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
CAPACITANCE
DESCRIPTION
Input /Output Capacitance
Input Capacitance
TEST CONDITIONS
V
I/O
=0V
V
IN
=0V
SYMBOL
C
I/O
C
IN
HMS51232J4A
MAX
28
20
UNIT
pF
pF
* NOTE
: Capacitance is sampled and not 100% tested
AC CHARACTERISTICS
(0oC
£
TA
£
70 oC ; Vcc = 5V
±
0.5V, unless otherwise specified)
TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
VALUE
0.V to 3V
3ns
1.5V
See below
Output Load (A)
+5V
Output Load (B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5V
480W
D
OUT
255W
30pF*
D
OUT
255W
480W
5pF*
* Including scope and jig capacitance
READ CYCLE
-10
PARAMETER
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Output
Output Enable to Low-Z Output
Chip Enable to Low-Z Output
Output Disable to High-Z Output
Chip Disable to High-Z Output
Output Hold from Address Change
Chip Select to Power Up Time
Chip Select to Power Down Time
SYMBOL
MIN
t
RC
t
AA
t
CO
t
OE
t
OLZ
t
LZ
t
OHZ
t
HZ
t
OH
t
PU
t
PD
10
-
-
-
0
3
0
0
3
0
-
MAX
-
10
10
5
-
-
5
5
-
-
10
MIN
12
-
-
-
0
3
0
0
3
0
-
MAX
-
12
12
6
-
-
6
6
-
-
12
MIN
15
-
-
-
0
3
0
0
3
0
-
MAX
-
15
15
7
-
-
7
7
-
-
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-12
-15
UNIT
URL: www.hbe.co.kr
Rev. 1.0 (May / 2003)
4
HANBit Electronics Co.,Ltd.