HANBit
HMS51232M4L
TIMING WAVEFORM OF WRITE CYCLE
( /WE Controlled )
t
WC
Address
t
AW
t
WR(5)
/OE
t
CW(3)
/CE
t
AS(4)
t
WP(2)
/WE
t
DW
t
DH
High-Z
Data Valid
t
OHZ
t
OW
High-Z
Data In
Data Out
TIMING WAVEFORM OF WRITE CYCLE
( /CE Controlled )
t
WC
Address
t
AW
t
CW(3)
t
WR(5)
/CE
t
AS(4)
/WE
t
WP(2)
t
DW
t
DH
Data Valid
Data In
Data Out
High-Z
Notes
( Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low : A write ends at the earliest transition among /CE going high and/WE going high.
t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the later of /CE going low to the end of write.
7
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
