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HSD16M32M4V-13 参数 Datasheet PDF下载

HSD16M32M4V-13图片预览
型号: HSD16M32M4V-13
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模块64Mbyte ( 16M ×32位), 72引脚SIMM基于16Mx8 , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 64Mbyte ( 16M x 32-Bit ) 72-Pin SIMM based on 16Mx8, 4Banks, 4K Ref., 3.3V]
分类和应用: 存储动态存储器
文件页数/大小: 10 页 / 106 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-A
SYM
PARAMETER
BOL
X
CLK cycle
time
CAS
7.5
latency=3
t
CC
CAS
-
latency=2
CLK to valid
output delay
CAS
5.4
latency=3
t
SAC
CAS
-
latency=2
Output data
hold time
CAS
2.7
latency=3
t
OH
CAS
-
latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to
output
in Hi-Z
CAS
5.4
latency=3
t
SHZ
CAS
-
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
7
-
6
6
6
6
t
CH
t
CL
t
SS
t
SH
t
SLZ
2.5
2.5
1.5
0.8
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
-
3
3
3
3
3
7
-
6
6
6
6
-
12
1000
0
10
8
10
1000
100
1000
10
MIN
MAX
MIN
MAX
MIN
MA
MIN
MAX
-8
-H
-L
HSD16M32M4V
-10
NOT
MIN
MAX
UNIT
E
10
1000
13
ns
1
7
ns
7
1,2
3
ns
3
3.5
3.5
2.5
1.5
1
7
ns
ns
ns
ns
ns
ns
3
3
3
3
3
2
2
7
ns
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Self
refres
h
Entry
Exit
CKE
n-1
H
H
L
H
CKE
n
X
H
L
H
X
/C
S
L
L
L
H
L
/R
A
S
L
L
H
X
L
/C
A
S
L
L
H
X
H
/W
E
L
H
H
X
H
D
Q
M
X
X
X
X
V
BA
0,1
A10/
AP
OP code
X
X
Row address
HANBit Electronics Co.,Ltd.
A11
A9~A0
NOTE
1,2
3
3
3
3
Bank active & row addr.
URL:
www.hbe.co.kr
REV 1.0 (August.2002)
-7-