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HFA5253CB 参数 Datasheet PDF下载

HFA5253CB图片预览
型号: HFA5253CB
PDF下载: 下载PDF文件 查看货源
内容描述: 800MHz的,超高速单片引脚驱动器 [800MHz, Ultra High-Speed Monolithic Pin Driver]
分类和应用: 驱动器接口集成电路光电二极管
文件页数/大小: 18 页 / 527 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HFA5253
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V
Differential Input Voltage (DATA and HIZ) . . . . . . . . . . . . . . . . . . 5V
Output Current Continuous (Note 1) . . . . . . . . . . . . . . . . . . . 160mA
Input Voltage (Any pin except as specified) . . . . . . . . . . V
CC
to V
EE
V
OUT
Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to -4V
V
HIGH
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
to -4V
V
LOW
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to V
EE
V
HIGH
to V
LOW
Voltage. . . . . . . . . . . . . 11V to 0V (V
HIGH
> V
LOW
)
Slew Rate Control Current (+SRC, -SRC) . . . . . . . . . . . . . . . . 12mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
20 Ld PSOP Package . . . . . . . . . . . . .
49
2
JC
Measured At Copper Slug Top Center with Infinite Heat Sink)
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(PSOP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 50
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below 160mA.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
3. Shorting the output to a voltage outside the specified range may damage the output.
Electrical Specifications
V
CC
= +11.2V; V
EE
= -6.4V; V
IH
= -0.9V; V
IL
= -1.75V; +SRC and -SRC are Not Connected, Unless
Otherwise Specified
(NOTE 4)
TEST
TEMP.
LEVEL
(
o
C)
A
A
V
HIGH
= -3.25V to +8.5V
V
LOW
= -3.5V to +8.25V
A
A
A
A
V
HIGH
V
LOW
At 500mV
At 250mV
A
A
A
B
B
V
IH
= 0V, V
IL
= -2V
V
IH
= 0V, V
IL
= -2V
V
IH
= 0V, V
IL
= -2V
V
IH
= 0V, V
IL
= -2V
V
HIGH
= -1V to 6.5V
V
LOW
= -1.5V to 6V
Fullscale = 5V, Note 6
Fullscale = 10.5V, Note 7
200mV
P-P
I
STEAL
= 0mA to 10mA, 5V Step
A
A
A
A
A
A
A
A
B
B
C
C
B
B
B
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
PARAMETER
INPUT CHARACTERISTICS
(V
HIGH
, V
LOW
)
V
HIGH
Input Offset Voltage
V
LOW
Input Offset Voltage
V
HIGH
Input Bias Current
V
LOW
Input Bias Current
V
HIGH
Voltage Range
V
LOW
Voltage Range
V
HIGH
to V
LOW
Differential Voltage Range
V
HIGH
/V
LOW
Interaction (Notes 5, 17)
TEST CONDITIONS
MIN
-150
-150
-50
-400
-3.5
-3.5
0
-
-
-3
0.4
-50
-700
-50
-400
0.95
0.95
-0.1
-0.8
-
1.0
-
-
1
-100
-120
TYP
-50
-50
110
-110
-
-
-
2
20
-
-
110
-300
70
-80
0.97
0.97
-
-
100
-
V
CC
- 0.35
V
EE
+ 0.35
-
-
-20
MAX UNITS
+50
+50
400
50
8.5
8.5
9.5
4
40
8
5
700
50
400
50
1
1
0.1
0.8
-
2.8
-
-
2
100
80
mV
mV
µA
µA
V
V
V
mV
mV
V
V
µA
µA
µA
µA
V/V
V/V
%
%
MHz
V/ns
V
V
ns
ps
ps
LOGIC INPUT CHARACTERISTICS
(DATA, DATA, HIZ, HIZ)
Logic Input Voltage Range
Logic Differential Input Voltage
DATA/DATA Logic Input High Current
DATA/DATA Logic Input Low Current
HIZ/HIZ Logic Input High Current
HIZ/HIZ Logic Input Low Current
TRANSFER CHARACTERISTICS
V
HIGH
Voltage Gain
V
LOW
Voltage Gain
V
HIGH
/V
LOW
Linearity Error
V
HIGH
/V
LOW
-3dB Bandwidth
Typical Slew Rate Control Range
+SRC Pin Voltage
-SRC Pin Voltage
SWITCHING CHARACTERISTICS
(Z
LOAD
= 16 inches of RG-58 Terminated with 50Ω)
Propagation Delay (Notes 8, 10)
Propagation Delay Match (Rising to Falling Edge,
Notes 8, 10)
Rising Edge Propagation Delay vs Duty Cycle
(Notes 9, 10)
91