HFA5253
The ultra high speed performance of the HFA5253 is a result
of UHF1 process leverages: low parasitic collector-to-
substrate capacitance of the bonded wafer, low collector-to-
base parasitic capacitance of the self-aligned base/emitter
technology and ultra high f
T
NPN (8GHz) and PNP (5.5GHz)
poly-silicon transistors.
Linearity Error is calculated for every data point in the range
and the worst case value is recorded.
V
HIGH
TO V
LOW
INTERACTION
V
HIGH
to V
LOW
Interaction is the change in V
OUT
(the
active channel) due to the inactive channel. V
HIGH
Interaction is measured as the change in V
OH
from 1V as
V
LOW
is moved from 0V to 750mV (V
LOW
is corrected for
gain and offset errors). V
LOW
Interaction is measured as
the change in V
OL
from 0V as V
HIGH
is moved from 1V to
250mV (with V
HIGH
corrected for gain and offset errors).
The minimum recommended difference between V
HIGH
and V
LOW
for the HFA5253 is 250mV.
Definition of Terms
V
OH
AND V
OL
Output High Voltage and Output Low Voltage. V
OH
is the
voltage at V
OUT
when the HIZ input is low and the DATA
input is high. V
OL
is the voltage at V
OUT
when HIZ is low and
DATA is low. The V
OH
and V
OL
levels are set with the V
HIGH
and V
LOW
inputs respectively.
OFFSET VOLTAGE
Offset Voltage is the DC error between the voltage placed on
V
HIGH
or V
LOW
and the resulting V
OH
and V
OL
. V
HIGH
Offset Voltage Error is obtained by measuring V
OH
with
V
HIGH
set to 0V and V
LOW
set to -2.5V to minimize
interaction effects. V
LOW
Offset Voltage Error is the
measurement of V
OL
with V
LOW
set to 0V and V
HIGH
set to
+7.5V.
GAIN
Gain is defined as the ratio of output voltage change to
input voltage change for a defined range. V
HIGH
Gain is
calculated with the following equation with V
LOW
fixed at
-2.5V:
V
OH
(
V
HIGH
at 6.5V
)
–
V
OH
(
V
HIGH
at -1V
)
V
HIGH
GAIN
= -----------------------------------------------------------------------------------------------------------------
-
7.5
Speed Advantage
Harris Pin Drivers on bonded-wafer technology definitely have
a speed advantage, coming from the low collector-to-
substrate capacitance and the high f
T
of the transistors. In
addition, the patented switching stage which fits uniquely to
Harris’ UHF1 process is another big contributor for the high
speed. This switching circuitry requires low series-resistance
NPN and PNP transdiodes available in UHF1. The rise and
fall times of the pin driver are largely determined by the slew
rate at the node VSO in the Schematic. The dominant
mechanism for the slew rate is the charging/discharging of the
collector-base capacitors of the transistors connected to the
node VSO. The charging/discharging currents are coming
from the switching stage current sources. The fast rise and fall
times are achieved because of the negligible collector-to-
substrate capacitance and the small base-collector
capacitance due to the self-aligned recessed oxide [2].
The DATA/DATA differential stage is not a factor for the speed if
its current sources have enough current not to bottleneck the
transient. However it should be noted that the propagation
delay mismatch is determined by this stage. Sufficient current is
allocated to the differential stage current sources to best match
the low-to-high and high-to-low transient propagation delays.
The specified load condition is a 16 inch 50Ω SMA cable with a
5pF capacitor at the end of the cable. This load simulates a
typical ATE environment for a DUT (Device Under Test) with
high impedance (>1kΩ) digital inputs. The rise/fall time for
HFA5253 with 5V
P-P
is typically 1.3ns. Pin drivers, built out of
the same circuit structure as shown in the Schematic, can be
made faster by trimming for a higher power supply current.
Currently the pin driver has rise/fall times of less than 1ns (10%
to 90% of 5V
P-P
) when I
CC
is trimmed to 125mA. Further
speed enhancement will be made if there is a market demand.
V
LOW
Gain is calculated in a similar manner:
V
OL
(
V
LOW
at 6V
)
–
V
OL
(
V
LOW
at -1.5V
)
V
LOW
GAIN
= -------------------------------------------------------------------------------------------------------------
7.5
V
HIGH
is held fixed at 7.5V. These Gain calculations minimize
the effects of Interaction and End Point Nonlinearities.
LINEARITY ERROR
Linearity Error is a measure of output voltage worst case
deviation from a straight line that has been corrected for
offset and 7.5V Gain. Linearity Error is given as a
percentage of fullscale and is done in two ranges, 5V and
10.5V. DATA is measure at 0.5V steps from -2.5V to 8V for
V
HIGH
and -3V to 7.5V for V
LOW
. The Linearity Error
equation is as follows for 10.5V fullscale:
V
OUT
(
IDEAL
)
=
V
IN
×
Gain
+
Offset
V
OUT
–
V
OUT
(
IDEAL
)
Linearity Error
= -------------------------------------------------------------
-
10.5
Basic ATE System Application
Figure 1 shows a pin driver in a typical per-pin ATE system. The
pin driver works closely with the Dual-Level Comparator and
the Active Load. When the DUT pin acts as an input waiting for
a series of digital signals, the pin driver becomes active with a
logic “0” applied on the HIZ pin and provides the DUT pin with
digital signals. When the DUT pin acts as an output, the pin
driver output will be in high impedance mode (HIZ) with a logic
The Linearity Error equation is as follows for 5V fullscale:
V
OUT
–
V
OUT
(
IDEAL
)
Linearity Error
= -------------------------------------------------------------
-
5
94
HARRIS [ HARRIS CORPORATION ]
