HT45RM03
Stack Register - STACK
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This is a special part of the memory which is used to save
the contents of the Program Counter only. The stack is or-
ganized into 8 levels and is neither part of the data nor
part of the program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the con-
tents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program coun-
ter is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
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If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
0
F
H
H
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1
1
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1
0
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Data Memory - RAM
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The data memory is designed with 226´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(192´8). Most are read/write, but some are read only.
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The special function registers include the indirect ad-
dressing registers (00H;02H), Timer/Event Counter 0
(TMR0;0DH), Timer/Event Counter 0 control register
(TMR0C;0EH), Timer/Event Counter 1 (TMR1:10H),
Timer/Event Counter 1 control register (TMR1C; 11H),
program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accu-
mulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register 0 (INTC0;
0BH), PWM higher-order byte register (PWMH;1AH),
PWM lower-order byte register (PWML;1BH), PWM
Control register (PWMC;1CH), Miscellaneous register
(MISC;1DH), the A/D result lower-order byte register
(ADRL;20H), the A/D result higher-order byte register
(ADRH;21H), the A/D control register (ADCR;22H), the
A/D clock setting register (ACSR;23H), the Compara-
tor Control register (CMPC;24H), the Operational Am-
plifier Control register (OPAC;25H), I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H).
The remaining space before the 26H or 40H is re-
served for future expanded usage and reading these
locations will get ²00H². The general purpose data
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
2
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0
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RAM Mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
Rev. 1.10
8
February 16, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
