HT48R0AA-1
Reset
The functional unit chip reset status are shown below.
There are three ways in which a reset can occur:
Program Counter
Interrupt
000H
·
·
·
RES reset during normal operation
RES reset during HALT
Disable
Clear
Prescaler
WDT time-out reset during normal operation
Clear. After master reset,
WDT begins counting
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
WDT
Timer/Event Counter
Input/Output Ports
Stack Pointer
Off
Input mode
Points to the top of the stack
V
D
D
V
D
D
m
0 . 0 1 F
TO PDF
RESET Conditions
RES reset during power-up
1
0
0
k
1
0
0
k
0
u
0
1
1
0
u
1
u
1
R
E
S
R
E
S
RES reset during normal operation
RES wake-up from HALT mode
WDT time-out during normal operation
WDT wake-up from HALT mode
m
0 . 1 F
1
0
k
B
a
s
i
c
H
i
-
n
o
i
s
e
R
e
s
e
t
R
e
s
e
t
m
0 . 1 F
C
i
r
c
u
i
t
C
i
r
c
u
i
t
Reset Circuit
Note: ²u² stands for ²unchanged²
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
V
D
D
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
R
E
S
t
S S T
S
S
T
T
i
m
e
-
o
u
t
An extra configuration option load time delay is added
during system reset (power-up, WDT time-out at normal
mode or RES reset).
C
h
i
p
R
e
s
e
t
Reset Timing Chart
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
R
E
S
C
o
l
d
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
S
y
s
t
e
m
R
e
s
e
t
Reset Configuration
Rev. 1.10
12
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
