HT48R0AA-1
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme ensures that each in-
struction is effectively executed in a cycle. If an instruc-
tion changes the contents of the program counter, such
as subroutine calls or jumps, in which case, two cycles
are required to complete the instruction.
Program Counter
-
PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T 1
T 2
T 3
T 4
T 1
T 2
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupts, the PC manipulates
the program transfer by loading the address corre-
sponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
*11
0
0
0
0
*10
0
0
0
0
*9
0
0
0
0
*8
0
0
0
0
*7
0
0
0
0
*6
0
0
0
0
*5
0
0
0
0
*4
0
0
0
0
*3
0
0
1
1
*2
0
1
0
1
*1
0
0
0
0
*0
0
0
0
0
Mode
Initial Reset
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter+2
*11
#11
S11
*10
#10
S10
*9
#9
S9
*8
#8
S8
@7
#7
S7
@6
#6
S6
@5
#5
S5
@4
#4
S4
@3
#3
S3
@2
#2
S2
@1
#1
S1
@0
#0
S0
Program Counter
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.10
6
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
