HI-3584
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3584 contains a 16-bit control register which is used to con-
figure the device. The control register bits CR0 - CR15 are loaded
from BD00 - BD15 when CWSTR is pulsed low. The control regis-
ter contents are output on the databus when SEL = 1 and RSR is
pulsed low. Each bit of the control register has the following func-
tion:
CR
Bit
CR0
STATUS REGISTER
The HI-3584 contains a 9-bit status register which can be interro-
gated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused
bits are output as zeros. The following table defines the status reg-
ister bits.
SR
FUNCTION
Receiver 1
Data clock
Select
Label Memory
Read / Write
STATE
0
1
0
1
DESCRIPTION
Data rate = CLK/10
Data rate = CLK/80
Normal operation
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
Disable label recognition
Bit
SR0
FUNCTION
Data ready
(Receiver 1)
STATE
0
1
DESCRIPTION
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
Receiver 1 FIFO holds less than 16
words
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
Receiver 2 FIFO holds less than 16
words
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
Transmitter FIFO not empty
Transmitter FIFO empty.
Transmitter FIFO not full
Transmitter FIFO full. FFT pin is the
inverse of this bit.
Transmitter FIFO contains less than
16 words
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
CR1
SR1
FIFO half full
(Receiver 1)
0
1
CR2
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable
32nd bit
as parity
Self Test
0
1
0
1
0
1
0
Enable label recognition
Disable Label Recognition
SR2
Enable Label recognition
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
The 429DO and 429DO digital
outputs are internally connected
to the receiver logic inputs
Normal operation
Receiver 1 decoder disabled
SR4
ARINC bits 9 and 10 must match
CR7 and CR8
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
SR6
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Data rate=CLK/10, O/P slope=1.5us
1
Data rate=CLK/80, O/P slope=10us
Data rate=CLK/10
Data rate=CLK/80
Scramble ARINC data
Unscramble ARINC data
SR8
Transmitter FIFO
half full
0
SR7
Transmitter FIFO
empty
Transmitter FIFO
full
0
1
0
1
SR5
FIFO full
(Receiver 2)
0
1
FIFO half full
(Receiver 2)
0
1
SR3
Data ready
(Receiver 2)
0
1
FIFO full
(Receiver 1)
0
1
CR3
CR4
CR5
1
CR6
Receiver 1
decoder
0
1
CR7
CR8
CR9
-
-
Receiver 2
Decoder
-
-
0
1
CR10
CR11
CR12
-
-
Invert
Transmitter
parity
Transmitter
data clock
select
Receiver 2
data clock
select
Data
format
-
-
0
1
0
1
0
1
0
1
CR13
CR14
CR15
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
