HI-3584
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, then "0" will appear in the 32nd bit.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
0
1
1
0
0
1
1
1
1
X
No
Yes
X
X
Yes
No
No
Yes
0
0
0
1
1
1
1
1
1
X
X
X
No
Yes
No
Yes
No
Yes
FIFO
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
TO PINS
SEL
EN
MUX
CONTRO
L
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
32 X 32
FIFO
CONTROL
BIT
/
16 x 8
LABEL
MEMORY
LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
CLOCK
CLK
32 BIT SHIFT REGISTER
DATA
BIT CLOCK
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
EOS
ONES
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
BIT CLOCK
START
NULL
SHIFT REGISTER
SEQUENCE
CONTROL
END
ZEROS
SHIFT REGISTER
ERROR
ERROR
DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
