HI-3584
PIN DESCRIPTIONS
SIGNAL
VDD
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
DESCRIPTION
+3.3V 5% (All three VDD pins on the chip-scale package must be connect to the same supply)
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
HF1
FIFO Half full, Receiver 1
D/R2
FF2
Receiver 2 data ready flag
FIFO full Receiver 2
HF2
FIFO Half full, Receiver 2
SEL
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
Data Bus control, enables receiver 1 data to outputs
EN2
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
POWER
I/O
0 V
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
INPUT
INPUT
OUTPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after
transmission and FIFO empty.
PL2
TX/R
HFT
FFT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
Transmitter FIFO Half Full
Transmitter FIFO Full
429DO
429DO
ENTX
CWSTR
RSR
“ONES” data output from transmitter
“ZEROS” data output from transmitter
Enable Transmission
INPUT
Clock for control word register
INPUT
Read Status Register if SEL=0, read Control Register if SEL=1
Master Clock input
CLK
INPUT
TX CLK
MR
OUTPUT
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
