HI-3584
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
CR2(3) ARINC word CR6(9) ARINC word
FIFO
matches
label
bits 9,10
match
CR7,8 (10,11)
The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, then "0" will appear in the 32nd bit.
0
1
1
0
0
1
1
1
1
X
No
Yes
X
0
0
0
1
1
1
1
1
1
X
X
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
X
No
Yes
No
Yes
No
Yes
X
Yes
No
No
Yes
TO PINS
SEL
MUX
CONTROL
BITS
R/W
CONTROL
32 TO 16 DRIVER
CONTROL
EN
HF
FF
D/R
32 X 32
FIFO
FIFO
LOAD
CONTROL
LABEL /
DECODE
COMPARE
CONTROL
BIT
/
CLOCK
OPTION
CONTROLBITS
CR0, CR14
CLK
CLOCK
16 x 8
LABEL
MEMORY
BIT
COUNTER
AND
END OF
SEQUENCE
32ND
BIT
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
BIT CLOCK
EOS
WORD GAP
TIMER
WORD GAP
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
ZEROS
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
