HI-6010
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SYMBOL
V
SS
WEF
CTS
TXC
HFS
MR
TXE
RXRDY
TXRDY
TXD0
TXD1
RXC
FCR
RXD0
V
DD
RXD1
D0
D1
D2
D3
D4
D5
D6
D7
WE
CS
C/D
RE
FUNCTION
POWER
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
POWER
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
0.0 Volts
DESCRIPTION
Error indication if high. Status register must be read to determine specific error.
Enables data transmission when low.
Source clock for data transmission. 4 times bit rate.
Hardware feature select.
Master reset, active high.
Low when transmission in progress.
High when data of received word is available.
High when data of a transmitted word may be input.
"Zeroes" data output of transmitter.
"Ones" data output of transmitter.
Source clock for data reception. 4 times bit rate.
First character received flag.
"Zeroes" data input to receiver.
5 Volts ±5%
"Ones" data input to receiver.
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
8 bit data bus input control active low.
Chip select, active low.
High for control or status register operations, low for data
8 bit data bus output control, active low.
The receiver logic is independent of the transmitter except in
the following ways:
1. Self Test
2. Parity Option
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with the transmitter clock.
The parity option affects both the receiver and transmitter.
Either both are operational or neither.
goes high for any one of three receiver errors. The status
register will show which of the three errors occurred:
Status Register Bit
Error
SR3
Received a parity error
SR4
Data Overwritten
SR5
Receiving sequence error
The possible Receiver sequence errors are:
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errors are cleared by MR or by reading the Status Register.
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
WEF is an error indicator. It goes high for a transmitter
"underwrite" (failure to keep up with byte loading) and pin 2
PIN 5 - HFS and the CONTROL REGISTER
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip. If HFS is low, the
HOLT INTEGRATED CIRCUITS
4-4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
