HI-6010
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VSS = 0V)
Supply Voltage:
Input Voltage Range
Input Current
VDD
VIN
IIN
-0.5V to +7.0V
-0.5V to VDD +0.5V
+10mA
Power Dissipation
PD
500mW
Operating Temperature Range: TA (Industrial)
-40°C to +85°C
TA (Hi temp & Military) -55°C to +125°C
Storage Temperature Range:
Lead Temperature
TSTG
-65°C to +150°C
Output Current
IOUT
+25mA
TLEAD
300°C for 60 Seconds
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These a re stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational se ctions of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
4.5
TYP
5
MAX
UNITS
Operating Voltage
Min. Input Voltage
Max. Input Voltage
Min. Input Current
Max. Input Current
Min. Output Voltage
VDD
VIH
VIL
IIH
5.5
V
V
(HI)
(LO)
(HI)
2.1
1.4
1.4
0.7
1.5
V
VIH = 4.9V
VIL = 0.1V
-1.5
2.7
µA
µA
V
(LO)
(HI)
IIL
VOH
VIH
IDD
CIN
IOUT = -1.5mA
IOUT = 1.8mA
f = 400KHz
Not tested
Max. Output Voltage (LO)
Operating Current Drain
Input Capacitance
0.7
2.8
20
V
0.8
mA
pF
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
DATA BUS TIMING - READ
(See Figure 1.)
Setup C/D to RD
tCDS
tCDH
tRC
50
0
ns
ns
ns
ns
ns
ns
Hold C/D to RD
Delay RD to Data
200
150
Delay Data Bus Hi-Z from RD
Setup CS to RD
tRD
tCSSR
tCSHR
0
0
Hold RD to CS
DATA BUS TIMING - WRITE
Set C/D to WE
(See Figure 2.)
tCDS
tCDH
0
0
ns
ns
ns
ns
ns
ns
ns
Hold C/D to WE
Setup Data Bus to WE
Hold Data Bus to WE
Setup CS to WE
tWDS
tDWH
tCSSW
tCSHW
tWP
200
100
0
Hold CS to WE
0
Pulse Width WE
200
TRANSMITTER TIMING
Delay TXE from CTS
Delay TXRDn from CTS
Delay TXRDY from last TXDn
Delay TXE from last TXDn
CTS pulse width
(See Figure 3.)
tCTL
tENDAT
tTXRDY
tTDTX
1.5
1
2.0
CLKS
CLK
16
CLKS
4
DATA BITS
CLK
tCPW
1
RECEIVER TIMING
Delay Last RXDn to RXRDY
(See Figure 4.)
tDR
3
CLKS
HOLT INTEGRATED CIRCUITS
4-12
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
