HI-6010
PIN 6 - MR
The chip is initialized whenever this pin goes high. The
Control Register is set to 0X10 0101 (CR7 - CR0). For the
transmitter this sets up 8 bit mode with the transmitter
enabled.
The transmitter logic is independent of the receiver except in
the followingways:
1. Self Test
2. Parity Option
PIN 7 - TXE
In self test the transmitter outputs route to the receiver inputs
internallyand theTXD0andTXD1outputs areinhibited.
Whenever a transmission begins, this pin goes low and
returnshighafter thetransmission is complete.
When parity is enabled, both the receiver and transmitter are
affected. Odd parity is automatically generated in the 32nd
bitifthisoptionis selected.
PIN 9 - TXRDY
Whenever TXRDY is a one, data may be written into the
transmitter buffer. In 8 bit "one byte at a time" mode, this pin
may bemonitoredtoindicatewhen towritethenext 8 bits.
HARDWARE CONTROL OF THE TRANSMITTER
PIN 2 - WEF
PIN 10 - TXD0 and PIN 11 - TXD1
This output goes high for 1 transmitter error and 3 receiver
errors. To determine which error is being flagged, read the
Status Register. Reading the Status Register also clears the
error flag. The transmitte r will not function until the error is
cleared. Itcanalso becleared by MR going high.
TXD0 will go high during a transmission if the data is zero.
TXD1 goes high if data is a one. When both pins are low this
is referred to as the Null state . Typically an ARINC
transmitter chip, such as the HI-8382, HI-8383, HI-8585 or
HI-8586 is connected to these pins to translate the 5 volt
levelsto theproper ARINCbus levels.
Theonly possible transmitter error is generated whenrunning
in 8 bit mode. Forthe transmitter this means loadingthe last3
bytes while the transmission is in progress. Failure to load a
byte before the previous byte's 8th bit is transmitted will
generatetheerror, indicatedby status bitSR7 set to a 1.
SOFTWARE CONTROLOF THETRANSMITTER
By writing into the Control Register and reading the Status
Register, the controlling processor can operate the
transmitter independent of the flags at the pins.
Transmissioncan beinitiatedby changing CR0from a 0 toa1
after the transmitter buffer has been loaded. Then the Status
Register may bemonitoredas follows:
PIN 3 - CTS
This pin is a hardware gate for transmissions. If the
transmitter buffer is loaded and Control Register bit CR0 is a
one, the only inhibitof the transmitter would be for CTS to bea
one. When taken low, transmission of an ARINC word is
enabled. It may be pulsedtoreleaseeachtransmitted word.
STATUS BIT VALUE
MEANING
SR0
SR2
SR7
0
1
Do not load the transmitter buffer
Ready to load the transmitter buffer
PIN 4 - TXC
0
1
Transmission in progress
Transmitter is idle
The data rate of transmission is controlled by this pin. This
clock must be4X thedesireddaterate.
0
1
No transmission error
8 bit mode only error for underwriting data
PIN 5 - HFS and the CONTROL REGISTER
This pinalong with theControl Register sets thefunctioningof
the chip. For thetransmitter:
Cabling Noise -The HI-6010 has TTL compatible inputs and
therefore they are susceptible to noise near ground. If the data
bus is passed by ribbon cable or the equivalent to the device
under test, it is possible to get significant glitches on the Master
Reset line. The problem will appear to be a pattern sensitive
failure. One cure is simply to adequately bypass Master Reset.
AnotheristobuffertheHI-6010inputsnearthechip.
CONTROL PROGRAM
PIN 5
VALUE
BIT NAME
VALUE
OPERATION
CR0
0
1
X
X
Transmitter is disabled
Transmitter is enabled
CR4
CR5
0
1
X
X
Not in self test
Self test enabled
Receiver Seems Dead - After Master Reset the HI-6010
receivermustseeawordgapbeforethefirstARINCdatabit.
0
1
0
1
0
0
1
1
8 bit mode + data in 32nd bit
8 bit mode + parity enabled
32 bit mode with parity enabled
8 bit mode with parity enabled
Error flags must be cleared by either a Status Register Read or
by a Master Reset. The operati on of either the transmitter or the
receiverisinhibiteduponerror.
HOLT INTEGRATED CIRCUITS
4-6
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
