HI-6010
PIN
SYMBOL FUNCTION
DESCRIPTION
1
VSS
WEF
CTS
TXC
HFS
MR
POWER
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
POWER
INPUT
I / O
0.0 Volts
2
Error indication if high. Status register must be read to determine specific error.
Enables data transmission when low.
Source clock for data transmission. 4 times bit rate.
Hardware feature select.
3
4
5
6
Master reset, active high.
7
TXE
RXRDY
TXRDY
TXD0
TXD1
RXC
FCR
RXD0
VDD
RXD1
D0
Low when transmission in progress.
High when data of received word is available.
High when data of a transmitted word may be input.
"Zeroes" data output of transmitter.
"Ones" data output of transmitter.
Source clock for data reception. 4 times bit rate.
First character received flag.
"Zeroes" data input to receiver.
5 Volts ±5%
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
"Ones" data input to receiver.
Data bus
D1
I / O
Data bus
D2
I / O
Data bus
D3
I / O
Data bus
D4
I / O
Data bus
D5
I / O
Data bus
D6
I / O
Data bus
D7
I / O
Data bus
WE
INPUT
INPUT
INPUT
INPUT
8 bit data bus input control active low.
Chip select, active low.
CS
C/D
High for control or status register operations, low for data
8 bit data bus output control, active low.
RE
goes high for any one of three receiver errors. The status
register will showwhich ofthethreeerrors occurred:
Status Register Bit
Error
The receiver logic is independent of the transmitter except in
the followingways:
SR3
SR4
SR5
Received a parity error
Data Overwritten
Receiving sequence error
1. SelfTest
2. Parity Option
The possible Receiver sequence errors are:
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with thetransmitter clock.
The parity option affects both the receiver and transmitter.
Eitherboth areoperational or neither.
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errorsareclearedby MRor byreading theStatus Register.
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
PIN 5 - HFS and the CONTROL REGISTER
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip. If H FS is low, the
WEF is an error indicator. It goes high for a transmitter
"underwrite" (failure to keep up with byte loading) and pin 2
HOLT INTEGRATED CIRCUITS
4-4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
