HI-8582, HI-8583
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-8582/
HI-8583 data bus during data read or write operations. The
following table describes this mapping:
BYTE 1
DATA
BUS
ARINC
BIT
CR15=0
ARINC
BIT
CR15=1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
SDI
9
SDI
31 30 32
Parity
1
Label
2
Label
3
Label
4
Label
5
Label
6
Label
7
Label
8
Label
1
Label
The HI-8582/HI-8583 guarantee recognition of these levels with a
common mode Voltage with respect to GND less than ±4V for the
worst case condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
HIGH SPEED
LOW SPEED
BIT RATE
100K BPS ± 1% 12K -14.5K BPS
PULSE RISE TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE FALL TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE WIDTH
5 µsec ± 5% 34.5 to 41.7 µsec
If the NFD pin is high, the HI-8582/HI-8583 accept signals that meet
these specifications and rejects signals outside the tolerances.
The way the logic operation achieves this is described below:
16 15 14 13 12 11 10
SDI
9
SDI
8
Label
7
Label
6
Label
5
Label
4
Label
3
Label
2
Label
BYTE 2
DATA
BUS
ARINC
BIT
CR15=0
ARINC
BIT
CR15=1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Parity
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the mini-
mum pulse width is guaranteed.
3. Each data bit must follow its predecessor by not less than 8
samples and no more than 12 samples. In this manner the bit
rate is checked. With exactly 1MHz input clock frequency, the
acceptable data bit rates are as follows:
ONES
V
DD
RIN1A
OR
RIN2A
GND
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
HIGH SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
NULL
V
DD
RIN1B
OR
RIN2B
GND
ZEROES
4. The Word Gap timer samples the Null shift register every 10
input clocks (80 for low speed) after the last data bit of a valid
reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
If NFD is held low, frequency discrimination is disabled and any
data stream totaling 32 bits is accepted even with gaps between
bits. The protocol still requires a word gap as defined in 4. above.
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
