HI-8582, HI-8583
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incomingARINC word.
CR2(3) ARINC word CR6(9) ARINC word
FIFO
OddParity Received
matches
label
bits9,10
match
The parity bit is reset to indicate correct parity was received
and the resulting word is written tothe receive FIFO.
CR7,8 (10,11)
Even Parity Received
0
1
1
0
0
1
1
1
1
X
No
Yes
X
0
0
0
1
1
1
1
1
1
X
X
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written tothe receive FIFO.
X
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be “0” when valid (odd parity)ARINC 429 words are received.
No
Yes
No
Yes
No
Yes
X
RETRIEVINGDATA
Yes
No
No
Yes
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
TO PINS
SEL
MUX
CONTROL
BITS
R/W
CONTROL
32 TO 16 DRIVER
CONTROL
EN
HF
FF
D/R
32 X 32
FIFO
LOAD
CONTROL
FIFO
LABEL /
DECODE
COMPARE
CONTROL
BIT
/
CLOCK
OPTION
CONTROLBITS
CR0, CR14
CLK
CLOCK
16 x 8
LABEL
BIT
MEMORY
COUNTER
AND
32ND
BIT
END OF
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
SEQUENCE
BIT CLOCK
EOS
WORD GAP
TIMER
WORD GAP
ONES
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
BIT CLOCK
END
START
SEQUENCE
CONTROL
NULL
ERROR
CLOCK
ZEROS
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
