HI-8582, HI-8583
TIMING DIAGRAMS (cont.)
STATUS REGISTER READ CYCLE
DON'T CARE
DON'T CARE
BYTE SELECT SEL
tSELEN
tENSEL
RSR
tDATAEN
DATA VALID
DATA BUS
tENDATA
CONTROL REGISTER READ CYCLE
BYTE SELECT SEL
DON'T CARE
DON'T CARE
tSELEN
tENSEL
RSR
tDATAEN
DATA VALID
DATA BUS
tENDATA
LABEL MEMORY LOAD SEQUENCE
tCWSTR
CWSTR
tCWHLD
tCWSET
DATA BUS
Set CR1=1
Label #1
Label #2
Label #16
Set CR1=0
tDWSET
tDWHLD
PL1 or PL2
tPL
tLABEL
LABEL MEMORY READ SEQUENCE
tCWSTR
CWSTR
tREADEN
EN1 or EN2
tCWHLD
tCWSET
tDATAEN
DATA BUS
Set CR1=1
Label #1
Label #2
Label #16
Set CR1=0
tENDATA
HOLT INTEGRATED CIRCUITS
9
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
