Notes:
output pulse. The tPHL propagation
delay is measured from the 50% point
on the trailing edge of the input pulse
to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase
by 100 ns.
6. CML is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (VO < 0.8 V). CMH is
the maximum rate of fall of the
common mode voltage that can be
sustained with the output voltage in the
logic high state (VO > 2.0 V).
7. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 is
recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying
an insulation test voltage ≥ 3000 V rms
for one second (leakage detection
current limit, II-O ≤ 5 µA). This test is
performed before the 100% production
test for partial discharge (Method b)
shown in the VDE 0884 Insulation
Characteristics Table, if applicable.
1. Derate total package power dissipa-
tion, PT, linearly above 70°C free air
temperature at a rate of 4.5 mW/°C.
2. Duration of output short circuit time
should not exceed 10 ms.
3. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
4. The tPLH propagation delay is
measured from the 50% point on the
leading edge of the input pulse to the
1.3 V point on the leading edge of the
1.0
5
0
V
T
= 4.5 V
V
I
= 4.5 V
CC
= 25 °C
CC
= 0 mA
V
= 4.5 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
CC
I = 5 mA
F
-1
-2
-3
-4
A
F
4
3
V
= 6.4 mA
O
V
= 2.7 V
O
I
= -2.6 mA
OH
2
1
0
-5
-6
V
= 2.4 V
O
-7
-8
I
= 6.4 mA
0.5
OL
0.1
0
-60 -40 -20
0
20 40 60 80 100
0
1.0
1.5
2.0
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
I
– INPUT CURRENT – mA
T
– TEMPERATURE – °C
A
F
A
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
Figure 2. Typical Logic High Output
Current vs. Temperature.
Figure 3. Output Voltage vs. Forward
Input Current.
V
CC
PULSE GEN.
t
= t = 5 ns
r
f
OUTPUT V
MONITORING
NODE
f = 100 kHz
10 % DUTY
CYCLE
O
5 V
HCPL-2200
V
V
= 5 V
O
1
2
3
4
8
7
6
5
CC
619 Ω
D
1
I
F
INPUT
MONITORING
NODE
D
D
D
2
3
4
C
15 pF
=
2
GND
5 kΩ
1000
R
1
C
=
1
T
= 25 °C
120 pF
A
100
10
I
F
+
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C AND
V
F
C
.
1
2
–
R
2.15 kΩ 1.10 kΩ 681 Ω
1.0
I
I
(ON) 1.6 mA 3 mA
5 mA
F
0.1
0.01
ALL DIODES ARE 1N916 OR 1N3064.
I
(ON)
F
INPUT I
F
50 % I (ON)
F
0 mA
0.001
1.1
1.2
1.3
1.4
1.5
t
t
PHL
PLH
V
– FORWARD VOLTAGE – V
V
F
OH
OUTPUT
1.3 V
V
O
V
OL
Figure 4. Typical Input Diode Forward
Characteristic.
Figure 5. Test Circuit for t
, t
, t , and t .
PLH PHL r f
1-128
HP [ HEWLETT-PACKARD ]
