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TABLE of Contents
6. Bus Interface
6.1 Bus Control General .........................................................................................6-1
6.1.1 Boot Width Selection ...........................................................................6-2
6.1.2 SRAM and ROM Bus Access..............................................................6-2
6.1.3 DRAM Bus Access ..............................................................................6-3
6.1.3.1 DRAM Row Address Bits Multiplexing.............................6-4
6.2 I/O Bus Control ................................................................................................6-5
6.2.1 I/O Bus Control....................................................................................6-6
6.3 Bus Control Register BCR ...............................................................................6-7
6.4 Memory Control Register MCR .....................................................................6-11
6.4.1 MEMx Parity Disable ........................................................................6-13
6.4.2 MEMx Wait Disable ..........................................................................6-13
6.4.3 MEMx Byte Mode .............................................................................6-13
6.4.4 Power Down.......................................................................................6-13
6.4.5 IRAM Refresh Test ............................................................................6-14
6.4.6 IRAM Refresh Rate ...........................................................................6-14
6.4.7 DRAM Type ......................................................................................6-14
6.4.8 Entry Table Map ................................................................................6-14
6.4.10 MEMx Bus Size ...............................................................................6-14
6.5 Input Status Register ISR ...............................................................................6-15
6.6 Function Control Register FCR......................................................................6-16
6.7 Watchdog Compare Register WCR................................................................6-18
6.8 IO3 Control Modes.........................................................................................6-18
6.8.1 IO3Standard Mode .............................................................................6-18
6.8.2 Watchdog Mode .................................................................................6-18
6.8.3 IO3Timing Mode ...............................................................................6-19
6.8.4 IO3TimerInterrupt Mode ...................................................................6-19
6.9 Bus Signals .....................................................................................................6-20
6.9.1 Bus Signals for the GMS30C2232 Processor ....................................6-20
6.9.2 Bus Signals for the GMS30C2216 Processor ....................................6-21
6.9.3 Bus Signal Description.......................................................................6-22
6.10 Bus Cycles ....................................................................................................6-27
6.10.1 MEMx Byte Mode =1 ......................................................................6-27
6.10.1.1 SRAM and ROM Single-Cycle Read Access.................6-27
6.10.1.2 SRAM and ROM Single-Cycle Write Access ................6-27
6.10.1.3 SRAM and ROM Multi-Cycle Read Access ..................6-28
6.10.1.4 SRAM Multi-Cycle Write Access ..................................6-28
6.10.2 MEMx Byte Mode =0 ......................................................................6-29
6.10.2.1 SRAM Single-Cycle Read Access ..................................6-29
6.10.2.2 SRAM Single-Cycle Write Access.................................6-29
6.10.2.3 SRAM Multi-Cycle Read Access ...................................6-30
HYNIX [ HYNIX SEMICONDUCTOR ]
