HYUNDAI MicroElectronics
GMS81508B/16B/24B
21. POWER FAIL PROCESSOR
The GMS815xxB has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration
register, PFDR, can enable or disable the power fail detect
circuitry. Whenever V
DD
falls close to or below power fail
voltage for 100ns, the power fail situation may reset or
freeze MCU according to PFR bit of PFDR. Refer to “7.4
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Note:
User can select power fail voltage level according to
PFV bit of PFDR at the OTP(GMS815xxBT) but must select
the power fail voltage level to define PFD option of “Mask
Order & Verification Sheet” at the mask chip(GMS815xxB).
Because the power fail voltage level of mask chip
(GMS815xxB) is determined according to mask option re-
gardless of PFV bit of PFDR
Note:
If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.
Power FailFunction
Enable/Disable
Level Selection
OTP
by PFD flag
by PFV flag
MASK
by PFD flag
by mask option
Table 21-1 Power fail processor
7
6
5
4
PFDR
R/W
3
PFV
R/W
2
PFD
R/W
1
PFR
R/W
0
PFS
ADDRESS: 0F9
H
INITIAL VALUE: ---- 1100
B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
Operation Mode
0: Normal operation regardless of power fail
1: MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Power Fail Voltage Selection Flag
0: 2.4V
1: 3.0V
Figure 21-1 Power Fail Voltage Detector Register
DEC. 1999 Ver 1.04
71
HYNIX [ HYNIX SEMICONDUCTOR ]
