GMS81508B/16B/24B
HYUNDAI MicroElectronics
20. RESET
The GMS815xxB have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-
On-chip Hardware
Program counter
G-flag
Peripheral clock
(PC)
(G)
Initial Value
(FFFF
H
) - (FFFE
H
)
0
Off
dog timer reset. Table 20-1 shows on-chip hardware ini-
tialization by reset action.
On-chip Hardware
Watchdog timer
Control registers
Power fail detector
Initial Value
Disable
Refer to Table 8-1 on page 25
Disable
Table 20-1 Initializing Internal Status by Reset Action
20.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start ex-
ecution as shown in Figure 20-2.
Internal RAM is not affected by reset. When V
DD
is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at addresses FFFE
H
- FFFF
H
.
A connection for simple power-on-reset is shown in Figure
V
CC
10kΩ
7036P
+
to the RESET pin
10uF
Figure 20-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
~
~
Oscillator
(X
IN
pin)
RESET
~
~
~
~
ADDRESS
BUS
DATA
BUS
?
?
?
?
FFFE FFFF Start
~ ~
~ ~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time
t
ST
= 62.5mS at 4.19MHz
Figure 20-2 Timing Diagram after RESET
~
~
RESET Process Step
1
f
MAIN
÷1024
MAIN PROGRAM
t
ST
=
x 256
20.2 Watchdog Timer Reset
70
DEC. 1999 Ver 1.04
HYNIX [ HYNIX SEMICONDUCTOR ]
