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HY57V281620HCLT-S 参数 Datasheet PDF下载

HY57V281620HCLT-S图片预览
型号: HY57V281620HCLT-S
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行x 2米X 16位同步DRAM [4 Banks x 2M x 16bits Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 13 页 / 97 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY57V281620HC(L)T
AC CHARACTERISTICS I
Parameter
(AC operating conditions unless otherwise noted)
-6
Symbol
Min
System Clock
Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
6
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
2.7
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
5.4
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
2.7
Max
Min
7
-7
Max
1000
Min
7.5
7.5
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
5.4
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
2.7
-K
Max
1000
Min
7.5
-H
Max
Min
8
1000
10
-
-
5.4
5.4
-
-
-
-
-
-
-
-
-
-
5.4
5.4
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
3
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
6
10
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
3
-8
Max
Min
10
1000
10
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
3
-P
Max
Min
10
1000
12
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
3
-S
Unit
Max
ns
1000
ns
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
ns
ns
ns
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Note
Clock High Pulse Width
Clock Low Pulse Width
Access Time
From Clock
CAS Latency = 3
CAS Latency = 2
Data-Out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data
Output in High-Z
Time
CAS Latency = 3
CAS Latency = 2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.2/Aug. 01
8