HY57V561620(L)T
AC CHARACTERISTICS I
-HP
Parameter
Symbol
Min
System clock cycle
time
Clock high pulse width
Clock low pulse width
Access time from
clock
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CLK to data output
in high Z-time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
7.5
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
3
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
6
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
3
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
6
Max
Min
7.5
1000
10
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
2
1
2
1
2
1
2
1
1
3
3
Max
Min
8
1000
10
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
2
1
2
1
2
1
2
1
1
3
3
Max
Min
10
1000
12
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
Max
Min
10
1000
ns
ns
ns
ns
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Max
ns
-H
-8
-P
-S
Unit
Note
Note :
1. Assume tR / tF (input rise and fall time ) is 1ns.
2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v
Revision 1.8 / Apr.01
HYNIX [ HYNIX SEMICONDUCTOR ]
