HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
DC CHARACTERISTICS II
(T
A
= 0 to 70
o
C)
Parameter
Sym-
bol
I
DD1
Test Condition
Burst length=1, One bank active
t
RC
≥
t
RC
(min), I
OL
=0mA
Speed
45
220
5
200
55
190
2
2
6
180
7
170
Unit Note
Operating Current
mA
mA
mA
1
Precharge Standby Cur- I
DD2P
CKE
≤
V
IL
(max), t
CK
= 15ns
rent
I
DD2PS
CKE
≤
V
IL
(max), t
CK
=
∞
in Power Down Mode
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= 15ns
Input signals are changed one time
during 2clks.
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
Precharge Standby Cur- I
DD2N
rent
in Non Power Down
Mode
I
DD2NS
17
mA
12
3
3
Active Standby Current I
DD3P
CKE
≤
V
IL
(max), t
CK
= 15ns
in Power Down Mode
I
DD3PS
CKE
≤
V
IL
(max), t
CK
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= 15ns
Input signals are changed one time
during 2clks.
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
t
CK
≥
t
CK
(min), I
OL
=0mA
All banks active
CL=3
290
260
280
250
mA
Active Standby Current I
DD3N
in Non Power Down
Mode
I
DD3NS
Burst Mode Operating
Current
Auto Refresh Current
I
DD4
I
DD5
40
mA
30
260
235
2
0.8
450
240
220
210
210
mA
mA
mA
mA
uA
1
2
3
4
5
t
RC
≥
t
RC
(min), All banks active
Normal
Self Refresh Current
I
DD6
CKE
≤
0.2V
Low Power
Super Low
Power
Note :
1. I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V643220DT(P) Series
4. HY57V643220DLT(P) Series
5. HY57V643220DST(P) Series
Rev. 0.3 / Sep. 2004
9
HYNIX [ HYNIX SEMICONDUCTOR ]
