HY57V651620B
PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
V SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V SS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity
S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA0,BA1
Bank Address
A0 ~ A11
Address
Row Address Strobe,
R A S , C A S, W E
Column Address Strobe,
Write Enable
LDQM, UDQM
DQ0 ~ DQ15
V
D D
/V
S S
V
D D Q
/V
S S Q
NC
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
R A S , C A S and W E define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 1.9/Apr.01
2
HYNIX [ HYNIX SEMICONDUCTOR ]
