1HY5DU281622ETP
SIMPLIFIED COMMAND TRUTH TABLE
Command
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
Entry
Self Refresh
Exit
CKEn-1
H
H
H
H
H
CKEn
X
X
X
X
X
CS
L
L
H
L
L
L
RAS
L
L
X
H
L
H
CAS
L
L
X
H
H
L
WE
L
L
X
H
H
H
CA
RA
L
H
L
H
H
L
X
X
ADDR
A10/
AP
OP code
OP code
X
BA
Note
1,2
1,2
1
V
V
1
1
1,3
1
1,4
1,5
1
1
1
1
H
X
L
H
L
L
CA
V
X
V
H
H
H
H
L
X
X
H
L
H
L
L
L
L
H
L
H
L
H
L
H
L
L
H
L
L
X
H
X
H
X
H
X
V
X
H
H
L
L
X
H
X
H
X
H
X
V
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
Precharge Power
Down Mode
Exit
H
L
X
1
1
1
1
L
H
Active Power
Down Mode
Entry
Exit
H
L
L
H
X
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note 6)
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before
entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from
Prechagre command.
3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+tRP).
4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery
Time(tWR) is needed to guarantee that the last data have been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
V
IHmin
~ V
ILmax
Rev. 1.0 / Oct. 2005
7
HYNIX [ HYNIX SEMICONDUCTOR ]
