H5GQ1H24AFR
1) Assert RESET# Low anytime when reset is needed.
2) Hold RESET# Low for minimum 100ns. Assert and hold NOP command.
3) Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of
CKE#; tATS and tATH must be met during this procedure. Keep EDC1 (MF=0) / EDC2 (MF=1) at the same
逻辑电平为中电初始化的设备功能并不能保证，如果在I / O宽度有
改变了。
4) Continue with step 9 of the power‐up initialization sequence.
V
DD
, V
DDQ
V
REFD / C
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CKE ＃
CK ＃
CK
CMD
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NOP
NOP
PRE
NOP
火车/ MRS
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交流
交流
ADR
DQ<31 ： 0> ，
DBI ＃ <3 ： 0>
EDC<3 ： 0>
WCK ＃
WCK
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所有银行
预充电
min. 100 ns
min. 200 μs
t
RP
步骤执行
13‐21 in Power‐up
顺序
注意事项： 1.交=任何命令
2. Device functionality is not guaranteed if x32/x16 mode is not the same as during power‐up initialization.
图4 ：初始化与稳定的力量
这份文件是一个普通的产品说明，如有变更，恕不另行通知。海力士半导体公司不承担任何
用于描述电路的责任。没有专利许可。
1.0版/十一月2009年
12
HYNIX [ HYNIX SEMICONDUCTOR ]
