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IC-NQCTSSOP20 参数 Datasheet PDF下载

IC-NQCTSSOP20图片预览
型号: IC-NQCTSSOP20
PDF下载: 下载PDF文件 查看货源
内容描述: 与信号校准13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION]
分类和应用: 转换器
文件页数/大小: 29 页 / 1077 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQC
preliminar y
Rev B1, Page 17/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
SIGNAL MONITORING and ERROR MESSAGES
SELAMPL
AMPL
Code
0x00
0x01
0x02
0x03
Code
0x04
0x05
0x06
0x07
Notes
Adr 0x0C, Bit 2
Adr 0x0C, Bit 1:0
Max ( |Sin| , |Cos| )
Voltage threshold V
th
0.60 x VDDA
0.64 x VDDA
0.68 x VDDA
0.72 x VDDA
Sin
2
+ Cos
2
V
thmin
V
thmax
0.20
0.9 x VDDA
0.30
0.9 x VDDA
0.40
0.9 x VDDA
0.50
0.9 x VDDA
Output amplitude*
1.0 V
pp
4.5 V
pp
1.5 V
pp
4.5 V
pp
2.0 V
pp
4.5 V
pp
2.5 V
pp
4.5 V
pp
Output amplitude*
1.4 V
pp
2.0 V
pp
2.6 V
pp
3.1 V
pp
Vss
Vth
Figure 13: Signal monitoring at minimum amplitude.
Vthmax
Vthmin
*) Entries are calculated with VDDA = 5 V.
Table 25: Signal amplitude monitoring
Figure 14: Sin
2
+ Cos
2
signal monitoring.
AERR
Code
0x00
0x01
Adr 0x03, Bit 1
Amplitude error message
disabled
enabled
Error Messages
Failure Mode
Table 26: Amplitude error
No error
Amplitude error
Frequency error
System error*
Warning**
Notes
*System error
**Warning
Line Signal SLO
Error bits E1, E0
for BiSS and SSI
CRC6 = 0
1, 1
0, 1
1, 0
0, 0
Error bits nE, nW
for BiSS and SSI
CRC6 = 1
1, nW
0, nW
0, nW
0, nW
nE, 0
FERR
Code
0x00
0x01
Notes
Adr 0x03, Bit 0
Excessive frequency error message
disabled
enabled
Input frequency monitoring is operational for
resolutions
16
NERR pulled low by external signal
Automatic step-back of resolution
Data output is deactivated and SLO
permanently high in case of: configuration
phase, invalid configuration, undervoltage.
Table 27: Frequency error
Configuration error
-
Always enabled
Table 30: Error messages
To enable the diagnosis of faults, the various types
of error are signaled at NERR using a PWM code as
given in the key on the left.
Two error bits are provided to enable communication
via the I/O interface; these bits can decode four differ-
ent types of error. If NERR is held at low by an external
source, such as an error message from the system, for
example, this can also be verified via the I/O interface.
Error are stored until the sensor data is output via the
I/O interface and then deleted. Errors at NERR are
displayed for a minimum of ca. 10 ms unless they are
deleted beforehand by a data output.
Table 28: Configuration error
Error Indication at NERR
Failure Mode
No error
Amplitude error
Frequency error
Configuration
Undervoltage
System error
Pin signal NERR
HI
LO/HI = 75 % (resp. HI for AERR = 0)
LO/HI = 50 % (resp. HI for FERR = 0)
LO
LO
NERR = low caused by an external error
signal
Table 29: Error indication at NERR