iC-NQC
preliminar y
Rev B1, Page 7/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item
No.
A04
Symbol
VCosc
Parameter
Conditions
Min.
Oscillator Frequency Power Sup- CFGOSC = 0x00
ply Dependance
Input Offset Voltage
Input Current
Common-Mode Input Voltage
Range
Differential Input Voltage Range
Saturation Voltage hi
Saturation Voltage lo
Rise Time
Fall Time
Permissible Load at A, B
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Pull-up Current in MA
Pull-down Current in SLI
Vt()hys = Vt()hi - Vt()lo
V() = 0 ... VDD - 1 V
V() = 1 ... VDD
0.8
300
-240
20
-120
120
-25
300
4
10
10
0
with read access to EEPROM
powering up with no EEPROM
CFGOSC = 0x00, TIMO = 0, TOA =0
1
20
2
0.8
Vt()hys = Vt()hi - Vt()lo
300
5
7
2
20
I() = 4 mA
V() = 0 ... VDD - 1 V
CL() = 50 pF
10
60.7
-600
-300
100
0.45
-75
60
2
1.5
50
Vs()hi = VDD - V(); I() = -4 mA
I() = 4 mA
CL() = 50 pF
CL() = 50 pF
TMA = 1 (calibration mode)
1
2
V() = Vcm()
V() = 0 V ... VDDA
-20
-50
1.4
0
Typ.
+9
Max.
%/V
Unit
Zero Signal Enable Inputs PZERO, NZERO
B01
B02
B03
B04
Vos()
Iin()
Vcm()
Vdm()
20
50
VDDA-
1.5
VDDA
0.4
0.4
60
60
mV
nA
V
V
V
V
ns
ns
MΩ
V
V
mV
µA
µA
MHz
MHz
ns
µs
ms
ms
µs
V
V
mV
ms
V
kHz
V
µA
ns
ms
ms
Incremental Outputs A, B, Z and I/O Interface Output SLO
D01 Vs()hi
D02 Vs()lo
D03 tr()
D04 tf()
D05 RL()
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
F01
F02
F03
F04
F05
Vt()hi
Vt()lo
Vt()hys
Ipu(MA)
Ipd(SLI)
fclk(MA)
tp(MA-
SLO)
tbusy_s
tbusy_r
tidle
t_tos
Vt()hi
Vt()lo
Vt()hys
tbusy()cfg
Vt()hi
I/O Interface Inputs MA, SLI
Permissible MA Clock Frequency SSI protocol
BiSS protocol
Propagation Delay:
MA edge vs. SLO output
Processing Time Single-Cycle
Data (delay of start bit)
Processing Time Register Ac-
cess (delay of start bit)
Interface Blocking Time
Timeout
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Threshold Voltage hi
Write/Read Clock at SCL
Saturation Voltage lo
Pull-up Current
Fall Time
Duration of Startup Configuration error free EEPROM access
RL(SLO)
≥
1 kΩ
EEPROM Interface Inputs SDA and Error Input NERR
EEPROM Interface Outputs SDA, SCL and Error Output NERR
G01 f()
G02 Vs()lo
G03 Ipu()
G04 ft()
G05 tmin()lo
G06 Tpwm()
G07 t()lo
Min. Duration Of Error Indication MA = hi, no BiSS access, amplitude or frequeny
at NERR (lo signal)
error
Cycle Duration Of Error Indica-
tion at NERR
fosc() subdivided 2
22
Duty Cycle Of Error Indication at signal duration low to high;
AERR = 0 (amplitude error)
NERR
FERR = 0 (frequency error)
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)
1
75
50
%
%
MΩ
G08 RL()
ICHAUS [ IC-HAUS GMBH ]
