ICM7561/7541/7521
C3 C2 C1 C0
0
0
0
0
DATA
(D11~D0:7561;D9~D0:7541;D7~D0:7521)
Data
FUNCTION
Input loaded into DAC, VO updated
Table 1. Serial Interface Input Word
CONTROL
C3 C2 C1 C0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DATA
D11~D2 D1 D0 (7561)
D9~D0 A1 A0 (7541)
D7~D0 A1 A0 (7521)
X
0 0
X
X
X
0
1
1
1
0
1
FUNCTION
DAC O/P, wakeup
Floating Output
Output is terminated with 1K
Output is terminated with100 K
Table 2. Power Down Mode Control
DETAILED DESCRIPTION
The ICM7561 is a 12-bit voltage output DAC. The ICM7541
is the 10-bit version of this family and the ICM7521 is the
8-bit version. These devices have a 16-bit input shift
register and the DAC has a double buffered digital input.
This family of DACs has a guaranteed monotonic behavior.
The operating supply range is from 2.7V to 5.5V.
Reference Input
The reference input accepts positive DC and AC signals.
The voltage at REFIN sets the full-scale output voltage of
the DAC. The reference input voltage range is from 0 to
VDD-1.5V. The impedance at this pin is very high (greater
than 10 M Ohm). The DAC output amplifier is configured in
a gain of 2 configuration. This means that the full-scale
output of the DAC will be 2x V
REF
. To determine the output
voltage for any code, use the following equation.
V
OUT
= 2 x (V
REF
x (D / (2
n
)))
Where D is the numeric value of DAC’s decimal input code,
V
REF
is the reference voltage and n is number of bits, i.e.
12 for ICM7561, 10 for ICM7541 and 8 for ICM7521.
Output Buffer Amplifier
The DAC has an output amplifier connected in a gain of 2
configuration. This amplifier has a wide output voltage
swing. The actual swing of the output amplifier will be
limited by offset error and gain error. See the Applications
Information Section for a more detailed discussion.
The output amplifier can drive a load of 2.0 K to V
DD
or
GND in parallel with a 500 pF load capacitance.
The output amplifier has a full-scale typical settling time of
8 s and it dissipates about 100 A with a 3V supply
voltage.
Serial Interface and Input Logic
This DAC family uses a standard 3-wire connection
compatible with SPI/QSPI and Microwire interfaces. Data is
always loaded in 16-bit words which consist of 4 control
bits (MSBs) followed by 12 bits (see Figure 3). The
ICM7561 uses the last two LSBs of the DAC data also for
power down control. The ICM7541 and ICM7521 have the
last 2 LSBs as power down control bits only and the data
which gets loaded into the DAC register starts at location
D0 (see tables 1 and 2).
Serial Data Input
SDI (Serial Data Input) pin is the data input pin for the DAC.
Data is clocked in on the falling edge of SCK which has a
schmitt trigger internally to allow for noise immunity on the
SCK pin. This specially eases the use for opto-coupled
interfaces.
The Chip Select pin which is the 3
rd
pin of 8 Lead MSOP
package is active low. This pin frames the input data for
synchronous loading and must be low when data is being
clocked into the part. There is an onboard counter on the
clock input and after the 16
th
clock pulse the data is
automatically transferred to a 16-bit input latch and the 4
bit control word (C3~C0) is then decoded and the
appropriate command is performed depending on the
control word (see Table 1, 2). Chip Select pin must be
pulled high (level-triggered) and back low for the next data
word to be loaded in. This pin also disables the SCK pin
internally when pulled high.
Rev. A6
ICmic reserves the right to change specifications without prior notice
6
ICMIC [ IC MICROSYSTEMS ]
