欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24012S 参数 Datasheet PDF下载

X24012S图片预览
型号: X24012S
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 14 页 / 271 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X24012S的Datasheet PDF文件第1页浏览型号X24012S的Datasheet PDF文件第2页浏览型号X24012S的Datasheet PDF文件第3页浏览型号X24012S的Datasheet PDF文件第4页浏览型号X24012S的Datasheet PDF文件第6页浏览型号X24012S的Datasheet PDF文件第7页浏览型号X24012S的Datasheet PDF文件第8页浏览型号X24012S的Datasheet PDF文件第9页  
X24012  
DEVICE ADDRESSING  
Following the start condition, the X24012 monitors the SDA  
bus comparing the slave address being transmit-  
Following a start condition the master must output the  
address of the slave it is accessing. The most significant  
ted with its slave address (device type and state of A0, A1  
and A2 inputs). Upon a correct compare the X24012  
four bits of the slave address are the device type  
identifier (see Figure 4). For the X24012 this is fixed as  
1010[B].  
outputs an acknowledge on the SDA line. Depending on the  
state of the R/W bit, the X24012 will execute a read  
or write operation.  
Figure 4. Slave Address  
WRITE OPERATIONS  
DEVICE TYPE  
IDENTIFIER  
Byte Write  
For a write operation, the X24012 requires a second  
address field. This address field is the word address,  
1
0
1
0
A2  
A1  
A0 R/W  
comprised of eight bits, providing access to any one of the  
128 words of memory. Note: the most significant bit  
DEVICE  
ADDRESS  
is a don’t care. Upon receipt of the word address the  
X24012 responds with an acknowledge, and awaits the  
3847 FHD F08  
next eight bits of data, again responding with an ac-  
knowledge. The master then terminates the transfer by  
The next three significant bits address a particular device.  
A system could have up to eight X24012 devices  
on the bus (see Figure 10). The eight addresses are defined  
by the state of the A0, A1 and A2 inputs.  
generating a stop condition, at which time the X24012 begins  
the internal write cycle to the nonvolatile memory.  
While the internal write cycle is in progress the X24012  
inputs are disabled, and the device will not respond to  
any requests from the master. Refer to Figure 5 for the  
address, acknowledge and data transfer sequence.  
The last bit of the slave address defines the operation to be  
performed. When set to one a read operation is  
selected, when set to zero a write operation is selected.  
Figure 5. Byte Write  
S
T
S
T
SLAVE  
ADDRESS  
WORD  
ADDRESS  
BUS ACTIVITY:  
MASTER  
A
R
T
DATA  
O
P
SDA LINE  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24012  
BUS ACTIVITY:  
X24012  
3847 FHD F09  
Figure 6. Page Write  
S
T
A
R
T
S
T
SLAVE  
ADDRESS  
BUS ACTIVITY:  
BUS  
MASTER  
WORD ADDRESS n  
DATA n  
DATA n–1  
DATA n+3  
MASTER  
O
P
SDA LINE  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
BUS ACTIVITY:  
X24012  
X24012  
3847 FHD F10  
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0  
5