X24012
Flow 1. ACK Polling Sequence
Page Write
The X24012 is capable of an four byte page write
operation. It is initiated in the same manner as the byte
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
write operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to three more words. After the receipt of each word,
the X24012 will respond with an acknowledge.
ISSUE
START
After the receipt of each word, the two low order address bits
are internally incremented by one. The high order
five bits of the address remain constant. If the master should
transmit more than four words prior to generating
ISSUE SLAVE
ADDRESS AND R/W = 0
the stop condition, the address counter will “roll over” and the
previously written data will be overwritten. As
ISSUE STOP
with the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
for the address, acknowledge and data transfer sequence.
ACK
RETURNED?
NO
YES
Acknowledge Polling
The disabling of the inputs, during the internal write
operation, can be used to take advantage of the typical
NEXT
OPERATION
A WRITE?
NO
5 ms write cycle time. Once the stop condition is issued to
indicate the end of the host’s write operation the
X24012 initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
YES
ISSUE STOP
PROCEED
condition followed by the slave address for a write
operation. If the X24012 is still busy with the write
ISSUE BYTE
ADDRESS
operation no ACK will be returned. If the X24012 has
completed the write operation an ACK will be returned
and the master can then proceed with the next read or write
operation (See Flow 1).
PROCEED
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the
3847 FHD F11
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
6
ICMIC [ IC MICROSYSTEMS ]
