X24165
Bus Timing
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
SDA IN
t
AA
t
DH
t
BUF
SDA OUT
6551 ILL F17
Write Cycle Limits
Symbol
t
WR
(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
6551 FRM T11.1
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
X24165 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
erase/program cycle. During the write cycle, the
Bus Timing
respond to its slave address.
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
6551 ILL F18
Notes: (5)Typical values are for T
A
= 25°C and nominal supply voltage (5V).
(6)t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
RESISTANCE (KΟ)
V
R
MIN
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
OUTPUTS
Will be
steady
Will change
from LOW
100
80
60
40
20
0
0
=
CC MAX
I
OL MIN
R
C
BUS
t
=1.8KΟ
R
MAX
=
MAX.
RESISTANCE
to HIGH
May change
from HIGH
to HIGH
Will change
from HIGH
to LOW
MIN.
RESISTANCE
to LOW
Changing:
State Not
Don’t Care:
Changes
Allowed
Known
Center Line
is High
20
40
60
80100120
6551 ILL F19
N/A
BUS CAPACITANCE (pF)
Impedance
13
ICMIC [ IC MICROSYSTEMS ]
