X24C01A
Current Address Read
Internally the X24C01A contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either a
read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of the
slave address with R/W set to one, the X24C01A
issues an acknowledge and transmits the eight bit word
during the next eight clock cycles. The read operation is
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
issues the start condition, and the slave address followed
by the word address it is to read. After the word
address acknowledge, the master immediately reissues the
start condition and the slave address with the R/W bit set to
one. This will be followed by an acknowledge from the
X24C01A and then by the eight bit word. The read operation
is terminated by the master; by not responding with an
acknowledge and by issuing a stop condition.
Refer to Figure 8 for the address, acknowledge and data
transfer sequence.
terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge and data
transfer.
Figure 7. Current Address Read
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
S
T
O
P
T
S
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
DATA
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Figure 8. Random Read
S
T
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
WORD
ADDRESS n
A
R
SLAVE
ADDRESS
S
T
O
P
T
S
A
C
A
C
T
S
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
DATA n
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K
K
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ICMIC [ IC MICROSYSTEMS ]
