X25256 – Preliminary Information
The X25256 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
™
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
PIN CONFIGURATION
8-Lead XBGA
HOLD
V
CC
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
1
2
3
4
8
7
6
5
S0
CS
V
SS
SI
SCK
WP
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
8-Lead SOIC
CS
SO
WP
V
SS
1
2
3
4
X25256
8
7
6
5
CC
HOLD
SCK
V
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
SI
edge of the clock input.
Chip Select (CS)
20-Lead TSSOP
CS
NC
1
2
3
4
5
6
7
8
9
10
SO
NC
NC
NC
NC
WP
NC
V
SS
20
19
18
17
16
X25256
15
14
13
12
11
V
CC
When CS is HIGH, the X25256 is deselected and the SO
output pin is at high impedance and unless an
internal write operation is underway, the X25256 will be in
the standby power mode. CS LOW enables the
X25256, placing it in the active power mode. It should be
noted that after power-up, a HIGH to LOW transition
NC
HOLD
NC
NC
NC
SCK
NC
NC
SI
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25256 status register are dis-
abled, but the part otherwise functions normally. When WP
is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is still
LOW will interrupt a write to the X25256 status reg-
PIN NAMES
Symbol
CS
SO
SI
SCK
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no affect on a write.
The WP pin function is blocked when the WPEN bit in the
status register is “0”. This allows the user to install
the X25256 in a system with WP pin grounded and still be
able to write to the status register. The WP pin func-
WP
V
SS
V
CC
tions will be enabled when the WPEN bit is set “1”.
HOLD
NC
www.icmic.com
Characteristics subject to change without notice.
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ICMIC [ IC MICROSYSTEMS ]
