X25256 – Preliminary Information
The Block Lock
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is
set, when set to a “0”, the latch is reset. This bit is
(BL0, BL1, and BL2) bits are nonvola- tile
and allow the user to select one of eight levels of
protection. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
controlled by hardware and cannot be written by the
WRSR instruction.
Status Register Bits
BL2
0
BL1
0
BL0
0
Array Addresses Protected
Array Lock
None
None
0
0
1
$6000–$7FFF (8K bytes)
$4000–$7FFF (16K bytes)
$0000–$7FFF (32K bytes)
$000–$03F (64 bytes)
$000–$07F (128 bytes)
$000–$0FF (256 bytes)
$000–$1FF (512 bytes)
Upper 1/4 (Q4)
Upper 1/2 (Q3, Q4)
Full Array (All)
First Page (P1)
First 2 Pages (P2)
First 4 Pages (P4)
First 8Pages (P8)
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Figure 1. Block Lock Configurations
bit itself, as well as the block-protected sections in the
memory array. Only the sections of the memory array
that are not block-protected can be written.
BL2-BL0
000
001
010
011
100
101
110
111
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it can- not
be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held LOW.
Thus an In Circuit Programmable ROM function can be
implemented by hardwiring the WP pin to Vss, writing to
and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
The table above defines the program protect status for
each combination of WPEN and WP.
1/2 Array
3/4 Array
All Array
Clock and Data Timing
The Write-Protect-Enable (WPEN) bit is available for the
X25256 as a nonvolatile enable bit for the WP pin.
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Programmable Hardware Write Protection
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
Read Sequence
When reading from the 2E
trol the Programmable Hardware Write Protect feature.
Hardware Write Protection is enabled when WP pin is
PROM memory array, CS is first
pulled LOW to select the device. The 8-bit READ instruction is
transmitted to the X25256, followed by the
LOW, and the WPEN bit is “1”. Hardware Write Protec-
tion is disabled when either the WP pin is HIGH or the
16-bit address of which the last 15 are used. After the
READ opcode and address are sent, the data stored in
WPEN bit is “0”. When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Lock bits and the WPEN
the memory at the selected address is shifted out on the SO
line. The data stored in memory at the next address
Characteristics subject to change without notice. 4 of 17
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