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X76F641AE 参数 Datasheet PDF下载

X76F641AE图片预览
型号: X76F641AE
PDF下载: 下载PDF文件 查看货源
内容描述: 安全串行闪存 [Secure Serial Flash]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 17 页 / 153 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X76F641  
Figure 1. X76F641 Device Operation  
Start Condition  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL is  
HIGH. The X76F641 continuously monitors the SDA and  
SCL lines for the start condition and will not respond to  
any command until this condition is met.  
LOAD COMMAND BYTE  
LOAD 8-BYTE  
PASSWORD  
A start may be issued to terminate the input of a control  
byte or the input data to be written. This will reset the  
device and leave it ready to begin a new read or write  
command. Because of the push/pull output, a start can-  
not be generated while the part is outputting data. Starts are  
inhibited while a write is in progress.  
VERIFY PASSWORD  
ACCEPTANCE BY  
USE OF PASSWORD ACK POLLING  
Stop Condition  
LOAD 2 BYTE ADDRESS  
All communications must be terminated by a stop condi-  
tion. The stop condition is a LOW to HIGH transition of  
SDA when SCL is HIGH. The stop condition is also used to  
reset the device during a command or data input  
sequence and will leave the device in the standby power  
mode. As with starts, stops are inhibited when outputting  
data and while a write is in progress.  
READ/WRITE  
DATA BYTES  
Twc OR DATA ACK POLLING  
Acknowledge  
7025 FM 03  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device, either  
master or slave, will release the bus after transmitting  
eight bits. During the ninth clock cycle the receiver will  
pull the SDA line LOW to acknowledge that it received the  
eight bits of data.  
Retry Counter  
The X76F641 contains a retry counter. The retry counter  
allows 8 accesses with an invalid password before any  
action is taken. The counter will increment with any com-  
bination of incorrect passwords. If the retry counter over-  
flows, all memory areas are cleared and the device is  
locked by preventing any read or write array password  
matches. The passwords are unaffected. If a correct  
password is received prior to retry counter overflow, the  
retry counter is reset and access is granted. In order to  
reset the operation of a locked up device, a special reset  
command must be used with a RESET password.  
The X76F641 will respond with an acknowledge after  
recognition of a start condition and its slave address. If  
both the device and a write condition have been  
selected, the X76F641 will respond with an acknowledge  
after the receipt of each subsequent eight-bit word.  
Reset Device Command  
The reset device command is used to clear the retry  
counter and reactivate the device. When the reset device  
command is used prior to the retry counter overflow, the retry  
counter is reset and no arrays or passwords are  
affected. If the retry counter has overflowed, all memory  
areas are cleared and all commands are blocked and the  
retry counter is disabled. Issuing a valid reset device  
command (with reset password) to the device resets and  
re-enables the retry counter and re-enables the other  
commands. Again, the passwords are not affected.  
Device Protocol  
The X76F641 supports a bidirectional bus oriented proto-  
col. The protocol defines any device that sends data onto  
the bus as a transmitter and the receiving device as a  
receiver. The device controlling the transfer is a master  
and the device being controlled is the slave. The master will  
always initiate data transfers and provide the clock for  
both transmit and receive operations. Therefore, the  
X76F641 will be considered a slave in all applications.  
Reset Password Command  
Clock and Data Conventions  
A reset password command will clear both arrays and set all  
passwords to all zero.  
Data states on the SDA line can change only during SCL  
LOW. SDA changes during SCL HIGH are reserved for  
indicating start and stop conditions. Refer to Figure 2 and  
Figure 3.  
3