X76F641
Figure 5. Acknowledge Polling
8th clk.
SCL
of 8th
‘ACK’
clk
‘ACK’
clk
8th
clk
pwd. byte
SDA
8th bit
‘ACK’
ACK or
no ACK
START
condition
7025 FM 10
READ OPERATIONS
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by the data
from n+1. The address counter for read operations
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 1FFFh for array 0,
Read operations are initiated in the same manner as write
operations but with a different command code.
Random Read
The master issues the start condition and a Read instruc-
tion and password, performs a Password Ack Polling, then
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
change. This limits random reads to a 256 byte block.
Therefore, with a single password cycle only a 256 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
lowed by a new command/address/password sequence.
A random read of the array 1 can access all locations with-
out another password command sequence.
1Fh for array 1), the counter “rolls o
ver” to address 0 and the
X76F641 continues to output data for each acknowl- edge
received. Refer to figure 7 for the address, acknowledge
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
read, a stop condition is generated without a preceding
acknowledge.
Figure 6. Random Read
Read
Password
Read
Password
7
Wait tWC
OR
COMMAND
0
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
S
Data Y
Data X
7025 FM 11
7
ICMIC [ IC MICROSYSTEMS ]
