ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Setting the Device Characteristics
The tables below show the settings which can be configured, as well as the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
CLK1 Output
Divide
10
2
8
4
5
7
3
6
Max. Frequency
5 V or 3.3 V (MHz)
40
200
50
100
80
55
135
67
Max. Frequency
Industrial Temp. Version
36
180
45
90
72
50
120
60
Table 2. CLK2 Output
F1
0
0
1
1
F0
0
1
0
1
CLK2
REF
F
REF
/2
OFF (Low)
F
CLK1
/2
Table 3. Output Duty Cycle Configuration
TTL
0
1
Duty Cycle Measured At
1.4 V
VDD/2
Recommended VDD
5V
3.3 V
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty
cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2.
Table 4. Crystal Load Capacitance
C1
0
0
1
1
C0
0
1
0
1
VDD = 5V
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 3.3V
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
MDS 307-01/02 F
In te grated Circuit Systems
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