ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and
the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be
OFF means that the following three bytes are sent to the ICS307:
00110001
Byte 1
10001010
Byte 2
00111011
Byte 3
As show in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this
data to the internal latch and the CLK output will lock within 10 ms.
Note:
If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and
the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended
that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended
changes on the output clocks.
AC Parameters for Writing to the ICS307
Parameter
t
SETUP
t
HOLD
t
W
t
S
Condition
Setup time
Hold time after SCLK
Data wait time
Strobe pulse width
SCLK Frequency
DATA
t
setup
C1
C0
TTL
t
hold
F1
R1
R0
Min.
10
10
10
40
Max.
Units
ns
ns
ns
ns
50
MHz
SCLK
t
w
STROBE
t
s
Figure 2. Timing Diagram for Programming the ICS307
External Components/Crystal Selection
The ICS307 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the ICS307 to minimize lead inductance. A 33Ω terminating resistor can be used in series with CLK1 and
CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be
used, where C is the value calculated from Table 4. For crystals with a specified load capacitance greater than C,
additional crystal capacitors may be connected from each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps should be = (C
L
-C)*2, where C
L
is the crystal load
capacitance in pF and C is the capacitance value from Table 4. These external capacitors are only required for
applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no
capacitors on either pin).
MDS 307-01/02 F
In te grated Circuit Systems
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